(1) Field of the Invention
The present invention relates to a frequency generator, and more particularly relates to a frequency generator with frequency jitter.
(2) Description of the Prior Art
FIG. 1 is a circuit diagram of a typical frequency generator. As shown, the frequency generator has a first current source I1 and a second current source I2 utilized for charging and discharging a capacitor C through a first switch SW1 and a second switch SW2 respectively. The first comparator COM1 has an inverted end receiving a first reference voltage V1 and an non-inverted end coupled to the capacitor C for comparing a voltage signal from the capacitor C and the first reference voltage V1. The second comparator COM2 has an non-inverted end receiving a second reference voltage V2 and an inverted end coupled to the capacitor C for comparing a voltage signal from the capacitor C and the second reference voltage V2. A SR flip-flop SRIN receives the output signals from the first comparator COM1 and the second comparator COM2 so as to generate a clock signal CLK utilized as the control signal for the first switch SW1 and the second switch SW2. As the clock signal CLK is high, the first switch SW1 is turned off and the second switch SW2 is turned on to have the second current source I2 discharging the capacitor C. As the gradually declined voltage level of the capacitor C reaches the second reference voltage V2, the second comparator COM2 generates a high-level output signal to have the clock signal CLK shifted to low. When the clock signal CLK is low, the first switch SW1 is turned on and the second switch SW2 is turned off to have the first current source I1 charging the capacitor C. As the gradually increasing voltage level of the capacitor C reaches the first reference voltage V1, the first comparator COM1 generates a high-level output signal to have the clock signal CLK shifted to high. Since the potential difference between the first reference voltage V1 and the second reference voltage V2 is constant and the current flows of the first current source I1 and the second current source I2 are fixed, the clock signal CLK with constant frequency can be generated.
For the above mentioned frequency generator, the clock signal CLK with frequency jitter can be achieved by jittering the current flows of the first current source I1 and the second current source I2 or the voltage levels of the first reference voltage V1 and the second reference voltage level V2. However, such methods are only suitable for the condition of regular and slow jittering, and cannot fulfill the demand of random and fast jittering.